(1) Field of the Invention
This invention relates generally to the method of forming electrically isolated regions on a semiconductor substrate and more particularly to the fabrication of dielectric isolation silicon structures (DIS).
(2) Description of the Prior Art
When several different electronic devices are to be formed on a single substrate, it is necessary to electrically isolate them from one another to reduce undesired interactions such as cross-talk, leakage, and electrical noise. What is often done is to form distinct regions on the silicon wafer with each region electrically isolated with a dielectric such as silicon dioxide. There are several methods described in the prior art to form these isolated regions. One method is the SIMOX (Separation by Implanted Oxygen) process wherein the dielectric region is formed by implanting oxygen ions to the required depth within the silicon substrate. The damage caused by ions to the silicon above the buried oxide is annealed out at reasonably high temperatures. Although a continuous silicon region is formed isolated from the rest of the wafer, this method requires additional steps to form isolation regions between devices fabricated later in this isolated region.
Another method is to bond two wafers, wherein one wafer has trenches formed which are then filled with a dielectric such as silicon dioxide and then planarized by chemical mechanical planarization method. The second wafer has a dielectric film formed on one surface. The two wafers are then bonded such that the dielectric films on both the wafers are in contact with each other. In the high temperature process that follows, the dielectric films reach close to glass transition temperatures and thereby get bonded. The top side of the structure is polished again to form isolated silicon structures surrounded by dielectric film. This method is somewhat complex and the process is not easy to control in manufacturing.
A third method of forming these isolated silicon structures is by forming porous silicon at a desired depth in a silicon wafer, implanted by a dopant, using wet anodization. The porous silicon is then oxidized Alternatively, epitaxial single crystal silicon is deposited over porous silicon which is later oxidized.
U.S. Pat. No. 5,091,330 describes a method of fabricating a dielectric isolated area. The isolated areas are formed by bonding two wafers, each wafer having a first and second surface. Trenches are formed on the first surface of the second wafer. A dielectric layer that can be planarized is then deposited within the trenches on this first surface. The two wafers are then placed together such that the dielectric layer on the second wafer and the first surface of the first wafer are bonded. A portion of the second surface of the second wafer is removed to at least to the bottom of each trench, leaving isolated silicon regions.
U.S. Pat. No. 5,466,631 describes a method for producing a semiconductor article comprising the steps of: preparing the first wafer having a non-porous silicon layer on porous silicon; bonding this wafer to a second wafer such that the non-porous surface is in contact with the second wafer; removing the porous silicon and transferring the non-porous part of silicon from the first wafer to the second wafer, dividing the transferred part of the non-porous silicon into several isolated regions. Porous silicon is formed by anodizing in HF solution and the non-porous silicon is formed by conventional epitaxy, bias sputtering, or molecular beam epitaxy methods.
U.S. Pat. No. 5,773,352 describes a fabrication process of bonded total dielectric isolation substrate. After forming grooves on one surface of a single crystal silicon wafer, a silicon dioxide film is formed followed by a poly-silicon on top of the oxide to fill and cover the grooves. After polishing this layer, another buffer poly-silicon layer is formed over the polished surface. On a second wafer, silicon dioxide layer is formed. Both the wafers are then laminated such that the buffer poly-silicon layer of the first wafer is mated with the oxide layer of the second wafer. After bonding, the composite structure is annealed to complete the bonding. The bonding between poly-silicon and silicon dioxide, according to the inventors, is of superior quality as compared to other bonding surfaces.
U.S. Pat. No. 5,950,094 describes a method for fabricating dielectric isolated silicon by anodizing a buried doped silicon layer through trenches formed between active areas to form porous silicon layer; oxidizing the porous silicon; and depositing a dielectric film in the trenches. An optional boron implant into the sidewalls of the isolated silicon regions to form lightly doped regions act as channel stops. The dielectric layer filling the trenches and the active areas are chemical-mechanically polished to form planar structures.